1. Field of the Invention
This invention relates to a shift register type memory. More particularly, it relates to a memory which employs a shift register type memory chip of the major-minor organization.
2. Description of the Prior Art
Typical memory chips of the shift register type are a magnetic bubble memory chip, a CCD (charge coupled device) memory chip, etc. In order to shorten the access time of a data, such shift register type memory chips adopt a known method of circuit arrangement which is called the major-minor organization.
FIG. 1 shows an arrangement plan of a memory chip of the major-minor organization. In the figure, circles denote bit positions of shift registers, and arrows denote shift directions. Minor loops m include l closed-loop shift registers m.sub.o - m.sub.l-1 of loop Nos. 0, 1, 2, . . . , j, . . . , and l-1), and each loop consists of n bits. Data blocks are stored in the minor loops. A major loop M is made up of a single closed-loop shift register. The number of bits of the major loop M is assumed to be m. The data blocks are put in and out through the major loop. A transfer gate G is a circuit which couples the major loop with the minor loops so as to exchange the data block between both the loops. A "write" circuit W and a "read" circuit R are provided over the major loop.
The memory chip having such an arrangement retains the data blocks by adopting a data structure in which the respective bits of each data block are dispersed to and stored in the corresponding bit positions of the minor loops. Referring to FIG. 1, the bit positions of the respective minor loops are places into which the data block of address O enters, the bit positions are places into which the data block of address 1 enters, . . . , and the bit positions are places into which the data block of address i enters. The leading bits of the respective data blocks enter into the minor loop No. 0, the first bits enter into the minor loop No. 1, . . . , and the j-th bits enter into the minor loop No. j. Accordingly, the bit position of the minor loop No. j receives the j-th bit of the data block of address i. The number B of bits constituting one data block is called the block length. In the case of FIG. 1, the number of the minor loops is l, and the number of bits of each loop is n. Therefore, n data blocks from address 0 to address (n-1), each of which has the block length B of l bits, can be stored. In case of the prior-art chips, the positional relationship of the addresses is illustrated in FIG. 1. That is, the bit position next to address 0 in each minor loop is address 1, the bit position next to address 1 is address 2, and so forth.
The memory chip adopting such a data structure conducts a memory operation as stated below. Now, let's consider a case of reading out the data block of address 2 (which shall hereinbelow be termed D.sub.2, and similarly, the data block of address i shall be termed D.sub.i) in FIG. 1. First, address 2 is shifted within each minor loop and is moved to an entrance and exit of the transfer gate. Subsequently, the transfer gate is operated to transfer the data block D.sub.2 to the major loop (this operation is called "transfer out" which is abbreviated to T.sub.out). The data block D.sub.2 is shifted in the major loop. When the data block D.sub.2 passes under the read circuit overlying the major loop, it is converted into an electric signal, which is transferred to the exterior. The shift of the data block D.sub.2 in the major loop is continued. When the data block D.sub.2 has travelled round the major loop and has come to entrances and exits of the transfer gate, the transfer gate is operated to return the data block D.sub.2 to addresses 2 which are the original positions in the minor loops (this operation is called "transfer in" which is abbreviated to T.sub.in). Thus, the "read" operation is completed.
The "write" operation for a data block is carried out similarly to the foregoing read operation. Now, consider a case of writing the data block into addresses 2. First, address 2 is shifted within each minor loop and is moved to the entrance and exit of the transfer gate. Subsequently, the old data block D.sub.2 already existing in addresses 2 is transferred out to the major loop, and it is shifted in the major loop. When this data block D.sub.2 passes under the write circuit overlying the major loop, the write circuit is operated to rewrite the old data block into the new one. When the new data block D.sub.2 has come to the entrances and exits of the transfer gate, it is transferred in, and it is returned to addresses 2. Thus, the write operation is completed.
In the above memory operation, while the data block D.sub.2 travels round the major loop, addresses 2 also move within the minor loops. Accordingly, in order that the data block D.sub.2 having traveled round the major loop may return to the original addresses 2 just at T.sub.in, the number of bits m of the major loop and the number of bits n of the minor loop may be held in the following relation: EQU n = m + 1 (1)
The reason why n is greater by 1 than m is that 1/2 bit for each of T.sub.in and T.sub.out, 1 bit in total, is required.
The memory chip of the major-minor organization is constructed and operated as thus far described.
In a memory employing such a shift register type memory chip of the major-minor organization, a case of successively reading or writing a series of data blocks extending over several successive addresses occurs frequently in the actual use. In such a case, the prior-art memory repeats one after another the read operation or the write operation of one data block as stated above. By way of example, in case where data blocks D.sub.1 to D.sub.3 of addresses 1 to 3 are to be read out, the data block D.sub.1 of address 1 is read out; upon completion of this operation, the data block D.sub.2 of address 2 is read out; and upon completion of this operation, the data block D.sub.3 of address 3 is lastly read out. In this manner, after the read operation or the write operation of one data block has been completed, the operation for the data block of the next address is initiated. Therefore, at most one data block exists in the major loop, and two or more data blocks cannot exist simultaneously. As the result, a long gap of time G arises between one data block and the succeeding data block of the next address. On account of the long gap of time G, the data transfer rate is low in the prior-art memory.
Here, let's consider the length of the gap G concretely as to the case of the memory chip in FIG. 1. FIG. 2 is an operation diagram in the case where two successive data blocks D.sub.1 and D.sub.2 in the memory chip of FIG. 1 are processed by the prior-art memory. The diagram has the time taken on the axis of abscissas, and indicates the points of time when the data blocks D.sub.1 and D.sub.2 are transferred out and transferred in and the points of time when they pass through a certain point A in the major loop. It is convenient that a period of time required for the data block to shift by 1 bit is used as the unit of time. Hereinafter, this unit shall be called the shift unit. FIG. 2 is also depicted with the shift unit. In the figure, T.sub.out is the point of time when the operation terminates, while T.sub.in is the point of time when the operation is initiated. It is convenient to choose as the point A in the major loop the point at which the minor loop No. 0 is coupled with the major loop (refer to FIG. 1), because in this case, the minor loop No. 0 stores the leading bits of the data blocks, and hence T.sub.out is at the same time the point of time when the leading bit of the data block begins to pass through the point A.
In FIG. 2, T.sub.out of the data block D.sub.1 as represented by T.sub.o (1) is taken as 0 (zero). Then, T.sub.in of the data block D.sub.1 as represented by T.sub.i (1) is equal to the number of bits m of the major loop. In general, the following relation holds between T.sub.out and T.sub.in of a certain data block D.sub.j, that is, T.sub.o (j) and T.sub.i (j): EQU T.sub.i (j) - T.sub.o (j) = m (shift units) (2)
The point of time t.sub.S (1) when the leading bit of the data block D.sub.1 starts passing through the point A agrees with the time T.sub.o (1), and hence, it is 0 (zero). The difference L between the point of time t.sub.S (j) when the leading bit of the data block D.sub.j starts passing through the point A and the point of time t.sub.E (j) when the last bit thereof ends passing through the point A shall be called the data block width. In FIG. 1, the number of the minor loops is l, and the respective minor loops are coupled with the major loop at intervals of 2 bits, so that the data block width L is given by: EQU L = 2 l - 1 (shift units) (3)
Accordingly, the point of time t.sub.E (1) when the last bit of the data block D.sub.1 passes through the point A is L + t.sub.S (1) = L. Betwen T.sub.in of the data block D.sub.1 as represented by T.sub.in (1) and T.sub.out of the data block D.sub.2 as represented by T.sub.o (2), the following relation holds: EQU T.sub.o (2) - T.sub.i (1) = 2 (shift units) (4)
The details of the value 2 are 1/2 shift unit for the T.sub.in operation of the data block D.sub.1, 1 shift unit for the shift of the data block D.sub.2 to the entrance and exit of the transfer gate, and 1/2 shift unit for the T.sub.out operation of the data block D.sub.2. Accordingly, T.sub.out of the data block D.sub.2 as represented by T.sub.o (2) is m + 2. After this point of time T.sub.o (2), quite the same operation as in the case of the data block D.sub.1 is repeated. The length of the gap G between the data blocks D.sub.1 and D.sub.2 is given by: EQU G = t.sub.S (2) - t.sub.E (1) (shift units) (5)
This gap G is given by (m - 2 - L). For example, in a case of a memory chip of 64 kilobits where m = 516 and l = 128, the gap G is a large value of 263.
As described above, in the case of successively processing the series of data blocks, the prior-art memory has the problem that the long time gap G arises between the two data blocks and that the data transfer rate is low on account of the gap G.
In order to eliminate the disadvantage, Japanese Patent Application Public-disclosure No. 51-44832 has proposed a major-minor organization in which data blocks are continuously transferred in or transferred out. The subject matter of the patent application for achieving such an object is that the product between the interval .DELTA.(shift units) of the respectively adjacent bits of a major loop containing information (in the foregoing example, .DELTA. = 2) and the number of minor loops, and the number of bits n of the minor loop have no common factor therebetween. This is a condition for continuously reading or writing a plurality of blocks without any gap between the blocks. According to this organization, the data blocks can be transferred in or out within the number of blocks enterable in the major loop and without causing any gap between the blocks. It is impossible, however, to transfer out or in a plurality of data blocks one after another without any blank between the blocks while a data having been transferred out from the minor loops is being transferred into the minor loops again.